Overview of the Gameboy Color hardware

Just like "GNU's Not Unix", it also applies that the Gameboy Color is not the traditional Gameboy. And this topic is solely about the GBC (Gameboy Color). So I'm digging through the documents known to me to extract the essentials that apply to the GBC only.

In another chapter, I presented a circuit layout but that was not for the GBC. The GBC has a 130 pin IC as CPU, and the GB and GBP have an 80 pin device.

Technical data

CPU 8 bit 8085 derivative
Speed 4.2 MHz (normal mode)
8.4 MHz (fast mode)
Work RAM 32 KB
Video RAM 16 KB
Link ports Wired, synchronous
Screen size 66 mm diagonal
Resolution 160 x 144 pixels
Colours 32768
Energy 3 Volts at less than 100 mA

Memory map

The processor of the Gameboy lacks all I/O instructions so everything is memory mapped. Which makes things a little bit more complicated than with straight Z80 designs. Still, for small applications, it's no big deal to assign part of the memory map to I/O space. Below is the memory map for the GBC:

       0000 +-----------+
            |           |  16 KB ROM, bank 0, fixed
            |           |  address range = [0000 .. 3FFF]
       4000 +-----------+
            |           |  16 KB ROM, bank 1 to n, swapped in and out by an MBC
            |           |  address range = [4000 .. 7FFF]
       8000 +-----------+
            |           |  8 KB video RAM, two banks, switchable by CPU
            |           |  address range = [8000 .. 9FFF]
       A000 +-----------+
            |           |  8 KB external RAM, inside the cart, if any is present
            |           |  The MBC must take care of possible bankswitching
            |           |  address range = [A000 .. BFFF]
       C000 +-----------+
            |           |  4 KB work RAM (bank 0)
            |           |  address range = [C000 .. CFFF]
       D000 +-----------+
            |           |  4 KB work RAM (bank 1..7)
            |           |  address range = [D000 .. DFFF]
       E000 +-----------+
            |           |  Mirror of address range [C000 .. DDFF]  
            |           |  Better not to be used
       FE00 +-----------+
            |           |  Sprite attribute table
       FEA0 +-----------|
            |           |  Do not use address range [FEA0 .. FEFF]
       FF00 +-----------+
            |           |  GBC system I/O ports
            |           |  address range [FF00 .. FF7F]
       FF80 +-----------+
            |           |  High RAM
            |           |  address range [FF80 .. FFFE]
       FFFF +-----------+
	    |           |  Interupt Enable register  
            |           |  address range [FFFF]
       0000 +-----------+
The address range consists of the addresses that are possible in that section of memory. The first number is the first possible address and the second number (the one after the two dots) is the LAST address of that range. It is INCLUSIVE. People aquainted with Modula-2 will be familiar with this notation.

CPU registers and flags

As opposed to a real Z80, the GBC CPU does not contain the IX, IY registers and also the auxilliary registerbank is missing. Which made a friend of mine conclude that it in fact was an 8085, but programmed with Zilog mnemonics. And since he writes assemblers for a hobby, I guess he's right. Check it all out at his website SB Projects.

Register Purpose Combines with to form
A Accumulator F AF
F Status flags A AF
B GP register C BC
C Counter B BC
D GP register E DE
E GP register D DE
H Pointer L HL
L Pointer H HL
SP Stackpointer None N/A
PC Instruction pointer None N/A

The F register has only four flags, of which two have meaning for technical programmers. As can be seen here:

Flag Bit position Shows
Z 7 The ZERO flag indicates if the most recent operation resulted in a zero result in the accumulator (A register). If the Z flag is "1", the result was "0"...
C 6 This bit reflects the state of the CARRY flag after the most recent operation that involved it.
H 5 The HALF CARRY flag is used in BCD arithmetic, which is not quite usefull for engineers.
N 4 The N flag is also BCD related.

The remaining bits [0 .. 3] are always set to "0".

"Missing" Z80 instructions

If the Gameboy CPU is a stripped Z-80 processor, the following instructions have been removed. If, on the other hand, the GBC CPU is a souped up 8085, the situation is different.

Opcode Explanation
08 EX     AF, AF'
10 DJNZ   PC + offset
22 LD     (nn), HL
2A LD     HL, (nn)
32 LD     (nn), A
3A LD     A, (nn)
CB3x SRL    reg
D3 OUT    (n), A
DB IN     A, (n)
DD group This is a group of instructions whose first byte is the 0DDh value. This is typical for instructions involving the IX registerpair. Since the GBC CPU does not have an IX register, these instructions are meaningless.
E0 RET    PO
E2 JP     PO, nn
E3 EX     (SP), HL
E4 CALL   PO, nn
E8 RET    PE
EA JP     PE, nn
EB EX     DE, HL
EC CALL   PE, nn
ED group This is a group of instructions whose first byte is the 0EDh value. The involved instructions are:
	 ADC    HL, rp                       SBC    HL, rp
	 IN     reg, (C)                     OUT    reg, (C)
	 NEG                                 IMx
	 RETI	                             RETN
	 CPI                                 CPIR
	 CPD	                             CPDR
	 IND                                 INDR
	 INI                                 INIR
	 LDD                                 LDDR
	 LDI                                 LDIR
	 OUTI                                OTIR
	 OUTD                                OUTDR
	 RLD                                 RRD
	 LD     A, R                         LD     R, A
	 LD     I, A                         LD     A, I
	 LD     rp, (addr)                   LD     (addr), BC
	 LD     (addr), DE                   LD     (addr), HL
F0 RET    P
F2 JP     P, nn
F4 JP     P, nn
F8 RET    M
FA JP     M, nn
FC CALL   M, nn
FD group This is a group of instructions whose first byte is the 0FDh value. This is typical for instructions involving the IY registerpair. Since the GBC CPU does not have an IY register, these instructions are meaningless.

"Extra" instructions of the Gameboy CPU

Apart from removing Z80 instructions from the Z80 (if Nintendo started out with a Z80 anyway, which is not so sure at all) some instructions were added as well. The following table shows these instructions with their opcodes:

Opcode Instruction Explanation
08 LD     (nn), SP Memory (nn) := SP
10 STOP Stop oscillator and put CPU in powersave mode
22 LDI    (HL), A Memory (HL) := A;
HL := HL + 1
2A LDI    A, (HL) A := Memory (HL);
HL := HL + 1
32 LDD    (HL), A Memory (HL) := A;
HL := HL - 1
3A LDD    A, (HL) A := Memory (HL);
HL := HL - 1
D9 RETI Return from interrupt. This is the last instruction from interrupt service routines.
E0 LD     (FF00 + n), A Address := FF00 + n;
Memory (Address) := A
E2 LD     (FF00 + C), A Address := FF00 + Register (C);
Memory (Address) := A
E8 ADD    SP, nn SP := SP + nn
nn = [-128 .. 127]
EA LD     (nn), A Memory (nn) := A
F0 LD     A, (FF00 + n) A := Memory (FF00 + n)
F2 LD     A, (FF00 + C) A := Memory (FF00 + C register)
F8 LD     HL, SP + dd HL := SP + dd
dd = [-128 .. 127]
FA LD     A, (nn) A := Memory (nn)
CB 3x SWAP   loc Exchange the values of the bitgroups [0..3] and [4..7] within the location 'loc', which can be any 8 bit register or the 8 bits addressed by the HL registerpair.

CPU comparison.

It doesn't really matter, if the GBC CPU is a descendant from the Z80 or an evolution from the 8080. But it makes me curious. So I want to make a comparison between the four involved CPU's: the Intel 8080, Intel 8085, Zilog Z80 and the Nintendo GBC. I will not compare the pinouts since neither of these chips was designed to be drop in replacements for eachother. Therefore I will use some kind of Kelvin scale. The Intel 8080 is zero Kelvin. It's the absolute bottom of what can be achieved. The rest goes up.

The table below contains all instructions relative to the 8080.

Processor: 8085 Z-80 GBC CPU
Additions: RIM
JR     disp
JR     <cond>, disp
RLC    reg
RRC    reg
RL     reg
RR     reg
SLA    reg
SRA    reg
SRL    reg
BIT    reg
RES    reg
SET    reg
DJNZ   disp
EX     AF, AF'
ED prefix group
    35 extra
DD prefix group
    24 extra
FD prefix group
    24 extra
JR     disp
JR     <cond>, disp
RLC    reg
RRC    reg
RL     reg
RR     reg
SLA    reg
SRA    reg
SRL    reg
BIT    reg
RES    reg
SET    reg

I think this makes the case clear. The GMB CPU is definitely not a souped up 8080 or 8085. It doesn't even come close. The table clearly shows that the GameBoy Color CPU is a somehwat stripped Z80. Let this close the discussion. The GBC CPU is more related to the Z-80 (or one of it's second sources) than to any Intel processor.

Page created 12 December 2005,