NSSBC : CPU module

The first module will be the CPU module. But not only the CPU will be on this board; since the DMA is very closely related to the CPU now is the best time to make the nssbc DMA ready. All potential busmasters on one single board makes the design a little easier than having to add a DMA later on a separate board.
Apart from the CPU and DMA there will be a reset controller and a clock generator. Plus an I/O decoder that decodes the I/O ports FF, FE, FD and FC. Port FF will be used for addressing the DMA chip. All four signals are brought out on the I/O connector.


NSSBC : Bus and expansion connector

On the right you see the expansion connector which is also the structure of the backplane system bus:

12345678
C +5V00FDDMACSFree Free FreeFreeFree
A 00FC00FE
 
910111213141516
C DMARDY+5VGND IORQMREQHALTNMIINT
A IEORDWRBAO WAITBREQ
 
1718192021222324
C D1D0D7D2+5VD6D5D3
A RESETM1RFSHGNDA0A1A2A3
 
2526272829303132
C D4CLKA15A14A13A12A11GND
A A4A5A6A7A8A9A10


Since you are familiar with the Z80 pinout you will see that I copied this same pinout in the structure of the expansion connector. This made routing the CPU board a lot easier. And the other boards seldomly use all signals, so there the layout of the signals is less critical.


NSSBC : The circuit drawing

Click the picture for a bigger view!

Above you see the cicuit drawing for the CPU board. It contains:

The Z80 DMA was designed to be as similar to the CPU as possible. This ensured that the DMA could simply be connected in parallel to the CPU. All DMA outputs are tristated (i.e. in the high impedance state) as long as the DMA is not the busmaster. So the CPU board is the most logical place to put a DMA chip. Probably we will never use it, but for the few occasions we do, we will be glad for our bold decision in this stage.

For the rest, the circuit is rather straightforward. The DMA is addressed at IO address FF. All decoded IO addresses are put on the expansion connector so they can be used elsewhere.


NSSBC : the status indicator

On the right we see the status indicator drivers. One 74HC14 gate buffers (and inverts) the signal. The other gate re-inverts the signal. The trick now, is to mount the LED and resistor in parallel to the second buffer gate. This results in

The buffered signals are: With the right polarity, the LED wil light green when the signal is '1' i.e. inactive and red when the signal is '0' or active. This serves two purposes


NSSBC : the board

Below are pictures of the routed board. The board was created with Eagle Light and hence measures 80 x 100 mm and uses 2 signal layers. The pincount is well under 300, the minimum drill size is 24 mils and the minimum trace width is 16 mils so every board fab can make this board. You may download the board and schematic files in the download section.

Solder side

Component side

Raw eagle view of the board


NSSBC : Wait wait wait!

As usual, things looked just fine, until the first add-on board was being designed. The memory board showed that the expansion connector is not in order. There are pins for BAO (Bus Acknowledge Out) and IEO (Interrupt Enable Out), but these signals may be used on an expansion board, so there must be a way out of the board onto the bus board, for the next expansion connector. So:

So the schematic will be changed and the board will be rerouted. Below are the results:

The circuit drawing (click the picture for a bigger view)

Raw eagle view of the board

Solder side

Component side

Things look promising now, but I will wait a few more days for yet other inconsistancies....

NSSBC : The board is routed, let's order some!

If you agree to the title of this section, 99% certain you are a C programmer. When the board is routable and the DRC shows no errors, you know one thing for sure: you're almost half way done! Now we come in the Wirthian state. As most people who have some knowledge of Pascal, Modula or Oberon know, real software is developed through a process called Stepwise refinements. And the surprise now is: so is hardware! We now enter the process of stepwise refinements. They take up the majority of the development time. In short:

REPEAT
  Look-To-The-Board;
  IF  Component-Is-Better-Off-Someplace-Else  THEN  
    Move-Component;
    Rerun-The-Attached-Traces;
    Optimize-Other-Traces
  END;
  Save-The-Board;
  IF  Routed-Trace-Looks-Weird	THEN  Rerun-The-Trace  END;
  IF  Via-Can-Be-Omitted	THEN  Rerun-The-Trace  END;
  Save-The-Board;
  Sleep-On-It (One-Night)
UNTIL satified
   
Yes, this is going to take time. That's why it's always good to have several boards in the making. Make sure to save the board file when one refinement works out good. Learn from the experiences in board I to improve board II (and the other way round). Take your time! It's a lot cheaper to wait another week with ordering than to cancel the job from the process queue in your PCB board house. IF they will do that at all. Otherwise you end up with a lot of unique beer spills! And the drilled holes in them make for lousy beer spills....

Refinements since the latest board published:

NSSBC : Minding my own business

So there I was, minding my own business. I was completing a lot of mini boards and in far states of composition I had:

Doing so I already discovered that the BAO and IEO signals needed special attention. These were signals that are either used or not used by a card. OK, in a sense, all signals are used, but not as in IEO and BAO. The latter two may be modified by a board! All other signals are just used, no more. So the backplane was modified to accomodate for BAO and IEO.

Then it was time for the bus buffer add-on board. And then the nickel dropped. Yes, this bus needs serious reworks. The memory board, the I/O boards and all were routable. Yet, the busbuffer board needed so much extra work that there is only one valid conclusion: the pinout of the bus is far from optimal. It was optimal in the sense that it mirrored the pinout of the Z80 processor. But for the rest.... lazyness always pays its toll.

So, instead of repairing a board with lots of room for improvements, I decided to do a major overhaul and use the knowledge and design decisions gained in later boards as input to the cpu and dma board: With this in mind, the z80ctrla design was renamed to z80ctrlb and everything that did not fit in the new goals was changed: This resulted in the following design:

The circuit drawing (click the picture for a bigger view)

The transzorb is a cheap power overload protector. It will clip off all voltages outside the specified voltage range. In this case, the range -1 to +6 Volts is accepted by the TransZorb (ICTE 5). For all other voltages, the TransZorb acts like a near perfect short circuit, thereby blowing the fuse of the power supply circuit.


NSSBC : selecting an I/O address

In the old design, the address of the DMA controller was fixed to FF. At the time that seemed logical. Or, at least, acceptable.

But after doing two other boards, the fxed I/O address of the DMA was not so acceptable anymore.

So I adopted the technique of the I/O boards: use a 688 and a dipswitch to make the I/O address user selectable. In the right, you see the circuit drawing:

When a DIP switch is 'ON' a '1' is supplied to the Qn input of the 74xx688 chip. When the switch is not ON, it is OFF and a '0' is presented to Qn.


Z80Ctrlb : the routed board

We're now 4 days later. Three days were filled with

This is a tedious procedure. And there's only one motto here: hang in! After the second 'ripup *' command of the day, quit the board, quit eagle and go do something else. Next day, start again. Re-place components. Redraw the circuit to fit your routing needs. And then, suddenly, you have only four airwires left. Which you cannot route manually. THAT is the time to start the auto router. Just let it have it's go and make the most stupid track you ever saw. Save the board and sleep on it. Next day: reroute tracks, one by one, to optimize the PCB. Make room, so you can create new tracks. You will start with a complete mess. And end with something that looks a lot less messy. This is how the board looks like now:




I use copper filling on both sides. Eagle is very convenient here. Just make a polygon (I just make a rectangle), assign it to a netname and press the ratsnest button. One side creates the '+5V' grid and the other side creates the 'GND' grid. You now have two metal grids shielding the PCB. And, very importantly, WIDE power pipes to and from the circuits. The signals are either 12 or 16 mils wide. The traces are optimized to create wide copper fill islands.

Check the webpage 'Eagle design' via the navigator frame

An addition

OK, I still got some DS1233 econoresets in stock. But how about all the normal people out there? Suppose they don't, what then? There are other reset controllers bu I bet they have a better pinout. So they will not fit. So I added a small classical reset circuit based on

The capacitor charges towards the supply voltage in roughly twice the RC time. In the case of a brownout or other power surge, the diode will make sure the capacitor discharges immediately, thereby generating a reset condition. This circuit is not as reliable as a DS1233, but in the good old days the DS1233 did not exist and still computers ran. So it cannot be all that bad.


Page created on 21 March 2011 and