Z80-Ctrlb : design

The design of this board is for the biggest part already covered in the gEDA section. Follow the 'gEDA NSSBC' link in the navigator. In fact, that was the Z80 Ctrla design. The b version has some minor improvements, like a better system bus and less superfluous components. The b-version fits in better with the I/O boards that were already designed for the a-version. Let's call it recursion.

Based upon the Z80 Ctrlb design, a board was created. Both circuit design and board layout were done with Eagle Lite. That's the freeware version intended for non commercial use. Why Eagle and not the free-as-in-free-beer gEDA package? Well, gEDA is a very fine CAD tool but it doesn't even come close to Eagle. Eagle is so powerful and intuitive to use, AND it has so many high level libraries, that it is miles ahead of the competition (in its market segment).


Z80-Ctrlb : The empty board

We start the board maker from within the circuit editor. Yes, create the board from the schematic. We get the usual screen with an 80 x 100 mm board in the lower right corner and a pile of components on the left. The trick is now to place the components such, that the board is easiest to route.Yes, eagle has an auto router. No, we're not going to use it. Why not? Most auto routers create boards that look like shit.

So, the routing will be mostly manual. Let's see which parts we have:

Connector This is a DIN 41612 style connector. These connectors are readily available, reliable, available in many formats and (very important) they are cheap. The connector is close to 100 mm long so we can place it only along one of the two 100 mm long sides. I chose to put it along the top edge of the board.
Power parts The power parts are passive parts that are on the board to do some basic power line filtering and manipulation. The 220 uF elco and one of the 100 nF caps are for general purpose buffering and need be installed close to the connector. Power and ground will be supplied by two power planes, so the position on the board is not critical I put them in the top left corner. This goes for the ICTE5 TransZorb as well.
HALT status LED The status LED for the HALT line should be placed such that the LED is close to an edge so the LED can be bent that it is radiating to the side of the board.
Reset circuitry There are only two customers for the Reset signal: the CPU, the DIN 41612 connector and the reset switch connector. So the DS1233 should be mounted close to the CPU. It will take power and ground from the power planes so only one wire goes out. Peace of cake.
Clock generator The clock generator package takes power from the power/ground grid, so the only 'wire' attached to it is the CLK output. Placement is not critical. Any place will be fine.
74xx688 This is the address decoder for the DMA circuit. In Z80Ctrla the DMA address was hardwired to FF. That looked fine, but it contradicted to the overall philosophy of flexibility. So the 74xx688 with an 8 position DIP switch was added. The 74688 takes 9 inputs: 8 address lines and the IORQ signal. So the 688 should be placed near an edge of the board, oriented such that the 8 address lines are easily accessible. The DMA has its lower 8 address line near one of the short sides, so that is the place where they will be taken off for the 688.
Z80 CPU The CPU (and DMA) are quite long and narrow so they should be oriented parallel to the DIN 41612 connector. The CPU is placed in the center of the board so that there is room to either side for placing clock and reset generators, and a lot of room above for wiring the connector signals towards the CPU.
Z80 DMA The DMA has one set of six lines that are in the same order as the CPU: A0 thru A5. So we save ourself to align the CPU and DMA such, that DMA pins 1 - 6 end up right below CPU pins 30 - 35. Twenty percent of the pins are done now. Just by following your gut feelings.

With these observations in mind, make a guess where to place your components. Think about it but not too long. Just put them somewhere on the board and try to route the signal. If this doesn't go very well, just enter the command 'ripup *' and juggle a few parts around. Look at the rats nest. After four days (with 6 to 10 hours per day) I had the placement as below. This was the fourth placement trial. The other three almost drove me crazy. If ever you get a similar feeling when routing a board, ripup all traces and juggle some components around.

In this case I used the circuit editor in one window and the board editor in another window and I rearranged the connections for the 688 such that they would come out easiest. In a 25 mil grid you can cram 7 signals between the pads of a 300 mil wide IC. So now 7 of the 8 address line shoot from below the 688 like a bullet from a barrel.

In the 600 mil wide space between the pads of the CPU and DMA, you can do whatever you like, except place components that are too thick or wide. But a small 100 nF disc capacitor will fit just fine, if necessary. Below is the component placement that proved to be successful

Laying the tracks

Imagine you're a rail road worker. Laying tracks from A to B. Sometimes you need a bridge. Or a viaduct. Straight and curvy stretches. Just start out with the easy ones. At start, do it with all layers active. But at a certain moment, the extra information of the package and the text becomes superfluous. At that moment: turn them off!

In the picture on the right you see that I turned off layers 21, 25 and 27. Sometimes it also pays off to disable layer 51. In effect, the only things that are left are copper related: tracks, pads, vias, keep-out zones.

Normally I am quite fond of the 300 mil 100 nF WIMA capacitors (not only because I still have a bag of them) since they can be placed on the far end of a 300 mil DIP package and the tracks can simply go underneath it. But since some DIP's were 500 mils wide and the power pins are rather far apart, either a wider body cap was needed, or a narrower bodied cap. So I chose for the latter. Look at the picture on the left for an example of this 100 mil capacitor.

The narrow cap has one very big advantage: it can be placed UNDERNEATH an IC socket. Just keep it floating above the circuit board for 5 mm (1/4") and after soldering bend it over. Or: mount it on the backside of the PCB. Please do bend it over there as well, for obvious reasons. For the rest: standard packages have been used for just about any part. Yes, all of them are through hole parts. We are doing this to clean up our spare parts boxes, filled with dozens of through hole components.


The tracks are laid

Below are some pictures of the (almost) finished board. Click on the small image to get a much more detailed version of it.

Red is the top layer and blue is the bottom layer. The DMA (lowermost DIP 40 package) has its decoupling capacitor underneath it.

When laying tracks keep in mind:


Some details

Here we see the spaghetti in the upper part of the board (between the Z80 CPU and the DNIN 41612 connector). On the right we see nicely spaced tracks. Straight, narrow and separated. That's good. On the left, however we see four signals that run parallel for quite some distance. This is not optimal but it is close to the power filter section and I needed space for some real copper flooding there. So these sigfnals were grouped. All of them are 12 mil signals on a 25 mil grid so spacing may be minimal but it's still 13 mils and that's not bad. And, the four signals are mainly slow signals:

Only the first signal (Write) is a fast acting signal. The other three are liable to almost never be used. So crosstalk is not to be expected from either of the four.

The white lines in the lower picture show continuous copper planes that may carry current and that are part of the ground plane. That was also one reason to group certain signals. The CLK signal has since been staightened.



On the right we see the 74xx688 address decoder. Required here were:

The DIP switch is mounted right above the 688 so the majority of signal lines are straight through connections. The rest is passed along between the pads of the circuit. So that is not a real problem. The problem comes from the address lines. How to get them to the right destinations?

The problem was solved by This solved the problems. 7 out of 8 address lines can be routed between the pads of the 74688 chip. That is enough. Eagle is great in this respect. Just keep the PCB CAD window open, besides the schematic editor window. All changes to the schematic are reflected in the circuit board in real time.


Mitering

Mitering is the replacement of 90 degree corners by either two 135 degree corners or by a single arc. 90 Degree angles should be avoided. Not because electrons behave like small marbles. And neither because of increased signal line impedance. 90 degree angles are better avoided for just one reason: they radiate a lot of noise. And receive noise as well. Read about it in the following file: mitering.pdf as published by the guys from UltraCad.

Eagle offers several kinds of mitering:

I decided to miter the full board with arcs. It looks quite nice and the board now looks like the mainboard of my ZX81 (which probably was hand routed anyway).


Pin and gate swapping

Many times, in the circuit drawing, you're working in logical mode: you work from top to bottom and from left to right. So in a comparator section (like here with the 74xx688) the MSB switch and MSB address line are either the upper position or the lower position and all other things to be compared are in a chronological way.

And then you are about to lay some track. Suddenly, the nicely formatted top to bottom and left to right hierarchy isn't that handy anymore. For the 688 it doesn't matter if the address line is on port P or port Q. As long as switch 'x' is compared to address line 'x', the operation remains the same. So the connections between the switch, the address bus and the 688 were redrawn to get a better copper real estate. As can be seen in the rightmost picture.

Something similar can be done when using gates of a logical device like a (N)AND, (N)OR, XOR or whatever other multiple input gate.


Page created on 3 April 2011 and