Z-8681 Microcomputer
Technical Manual
November 1984

Chapter V: Instruction set

5.1 Functional summary.

Z8 instructions can be divided functionally into the following eight groups:

• Load
• Arithmetic
• Logical
• Program control
• Bit manipulation
• Block transfer
• Rotate and shift
• CPU control

Load instructions.

Arithmetic instructions.

Logical instructions.

Program control instructions.

Bit manipulation instructions.

Block transfer instructions.

Rotate and shift instructions.

CPU control instructions.

5.2 Processor flags.

The FLAGS register (R252) informs the user about the current status of the Z8. The flags and their bit positions in the FLAGS register are shown in figure 5.1:

R252 FLAGS register

The Z8 flag register contains six bits of status information which are set or cleared by CPU operations. Four of these (C, V, Z and S) can be tested for use with conditional JUMP instructions. Two flags (H and D) cannot be tested and are used for BCD arithmetic.
The two remaining bits in the FLAGS register (F1 and F2) are available to the user but they must be set or cleared by instruction and are not usable for conditional jumps.

As with bits in the other control registers, FLAGS register bits can be set or cleared by software. However, this is only possible when instructions are used that do not influence the FLAGS register as an outcome of their own execution.

5.2.1 CARRY flag (C).

The CARRY flag is set to '1' whenever the result of an arithmetic operation generates a carry out of or borrow into the high order bit 7; otherwise the CARRY flag is reset to '0'.
Following rotate and shift instructions, the CARRY flag contains the last value shifted out of the specified register.

An instruction can set, reset or complement the CARRY flag. IRET changes the value of the CARRY flag when the saved FLAGS register is restored.

5.2.2 ZERO flag (Z).

For arithmetic and logical operations, the ZERO flag is set to '1' if the result of that operation is ZERO. Otherwise the ZERO flag is set to '0'.
If the result of testing bits in a register is zero, the ZERO flag is set to '1'; otherwise the flag is cleared.
If the result of a rotate or shift instruction is zero, the ZERO flag is set to '1'; otherwise the flag is set to '0'.

IRET changes the value of the CARRY flag when the saved FLAGS register is restored.

5.2.3 SIGN flag (S).

The SIGN flag stores the value of the most significant bit of a result following arithmetic, logical, rotate or shift operations.
When performing arithmetic operations on signed numbers, binary 2's complement notation is used to represent and process information. A positive number is identified by a '0' in the most significant bit position, and therefore the SIGN flag is also ZERO.
A negative number is identified by a '1' in the most significant bit position and therefore the SIGN flag is also ONE.

IRET changes the value of the CARRY flag when the saved FLAGS register is restored.

5.2.4 Overflow flag (V).

For signed arithmetic, rotate and shift operations, the OVERFLOW flag is set to '1' when te result is greater than the maximum possible positive number (i.e. >127) or smaller than the maximum possible negative number (i.e. <-128) that can be represented in two's complement form. The flag is reset to ZERO if no overflow occurs.

Following logical operations, the OVERFLOW flag is set to '0'.

IRET changes the value of the CARRY flag when the saved FLAGS register is restored.

5.2.5 Decimal adjust (D).

The DECIMAL ADJUST flag is used by for BCD arithmetic. Since the algorithm for correcting BCD operations is different for addition and subtraction, this flag specifies what type of instruction was last executed so that the subsequent DA (Decimal adjust) operation can function properly. Normally, the DECIMAL ADJUST flag cannot be used as a test condition.
After a subtraction, the DECIMAL ADJUST flag is set to '1' and following an addition it is cleared to '0'.

IRET changes the value of the CARRY flag when the saved FLAGS register is restored.

5.2.6 Half carry flag (H).

The HALF CARRY flag is set to '1' whenever an addition generates a carry out of bit 3 (BCD overflow), or a subtraction generates a borrow into bit 3. The HALF CARRY flag is used by the Decimal adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct BCD result. As in the case of the DECIMAL ADJUST flag, the user does not normally access this flag.

IRET changes the value of the CARRY flag when the saved FLAGS register is restored.

5.3 Condition codes.

Flags C, Z, S and V control the operation of the conditional jump instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4 bit field called the CONDITION CODE (cc), which forms bits 4-7 of the conditional instructions. Section 5.4.2 lists the conditional codes and the flags settings they represent.

5.4 Notation and binary encoding.

In the detailed instruction descriptions that make up the rest of this chapter, operands and status flags are represented by a notational shorthand. Operands (condition codes and address modes) and their notations are as follows:

Additional symbols are:

Assignment of a value is indicated by the symbol ':='. For example:

   dst := dst + src
   

   dst (7)
   

5.4.1. Assembly langage syntax.

For proper instruction execution, Z8 PLZ/ASM assembly language syntax requires that "dst, src" be specified, in that order. The following instruction descriptions show the format of the object code produced by the assembler. This binary format should be followed by users who prefer manual program coding or who intend to implement their own assembler.

Example: If the contents of register 0x43 and 0x08 are added and the result stored in 0x43 the assembly syntax and resulting object code are:

In general, whenever an instruction format requires an 8 bit register address, that address can specify any register location in the range [0..127], [240..255] or a working register [R0..R15]. If, in the above example, register 0x08 is a working register, the assembly syntax and resulting object code will be:

For a more complete description of assembler syntax refer to the Z8 PLZ/ASM assembly language manual (publication nr 03-3023-03) and ZSCAN 8 User's tutorial (publication nr 03-8200-01).

5.4.3 Condition codes and flag settings.

The condition codes and flag settings are summarized in the following tables. Notation for the flags and how they are affected are as follows:

        C       Carry flag              0       cleared to ZERO
        Z       Zero flag               1       set to ONE
        S       Sign flag               *       set or cleared according
                                                to operation
        V       Overflow flag
        D       Decimal adjust flag     -       not affected
        H       Half-carry flag         X       undefined

   

Condition codes

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